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enhanced a/d type 8-bit otp mcu ht46r016/HT46R017 revision: v.1.00 date: ???? 1?? ?01? ???? 1?? ?01?
rev. 1.00 ? ???? 1?? ?01? rev. 1.00 3 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu table of contents eates cpu feat?res ......................................................................................................................... 5 periphera? feat?res ................................................................................................................. 5 genera? description ........................................................................................ ? se?ection tab?e ................................................................................................. ? b?ock diagram .................................................................................................. ? pin assignment ................................................................................................ ? pin description ................................................................................................ 7 abso??te maxim?m ratings ............................................................................ 9 d.c.characteristics .......................................................................................... 9 a.c. characteristics ....................................................................................... 10 adc characteristics ...................................................................................... 10 lvr characteristics ........................................................................................ 11 power-on reset characteristics .................................................................... 11 s?stem architect?re ...................................................................................... 1? c?ocking and pipe?ining ......................................................................................................... 1? program co?nter C pc .......................................................................................................... 13 stack ..................................................................................................................................... 13 arithmetic and logic unit C alu ........................................................................................... 14 progam memor? ............................................................................................. 15 str?ct?re ................................................................................................................................ 15 specia? vectors ..................................................................................................................... 1? look-? p tab?e ........................................................................................................................ 1? data memor? .................................................................................................. 18 str?ct?re ................................................................................................................................ 18 specia? p?rpose data memor? ............................................................................................. 19 specia? f?nction register ............................................................................. ?0 indirect addressing registers C iar0 ? iar1 ......................................................................... ?0 memor? pointers C mp0? mp1 .............................................................................................. ?0 acc?m?? ator C acc ............................................................................................................... ?1 program co?nter low register C pcl .................................................................................. ?1 stat? s register C status .................................................................................................... ?1 inp?t/o?tp?t ports and contro? registers ............................................................................. ?3 s?stem contro? registers C ctrl0? ctrl1 ......................................................................... ?3 wake- ?p f? nction register C pawk ..................................................................................... ?4 p??? -high registers C papu? pbpu ....................................................................................... ?4
rev. 1.00 ? ???? 1?? ?01? rev. 1.00 3 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu oscillator ........................................................................................................ 25 s?stem osci??ator overview .................................................................................................. ?5 system clock confgurations ................................................................................................ ?5 externa? cr?sta?/resonator osci??ator C hxt ........................................................................ ?5 interna? rc osci??ator C hirc ............................................................................................... ?? interna? low speed osci??ator C lirc ................................................................................... ?? power down mode and wake-up .................................................................. 27 entering the power down mode ........................................................................................... ?7 standb? c?rrent considerations ........................................................................................... ?7 wake- ?p ................................................................................................................................ ?8 watchdog timer ............................................................................................. 29 watchdog timer c ?ock so?rce .............................................................................................. ?9 watchdog timer contro ? register ......................................................................................... ?9 watchdog timer operation ................................................................................................... 30 reset and initialisation .................................................................................. 32 reset f?nctions .................................................................................................................... 3? reset initia? conditions ......................................................................................................... 35 input/output ports ......................................................................................... 37 p???-high resistors ................................................................................................................ 37 port a wake- ?p ..................................................................................................................... 37 i/o port contro? registers ..................................................................................................... 38 pin-shared f?nctions ............................................................................................................ 38 i/o pin str?ct?res .................................................................................................................. 39 programming considerations ................................................................................................ 40 timer/event counter ..................................................................................... 41 confguring the timer/event counter input clock source .................................................... 41 timer registers C tmr0 ? tmr1 ........................................................................................... 4? timer contro ? registers C tmr0c? tmr1c .......................................................................... 4? timer mode ........................................................................................................................... 44 event co?nter mode ............................................................................................................. 44 p??se width capt?re mode ................................................................................................... 45 presca?er ............................................................................................................................... 4? pfd f?nction ........................................................................................................................ 4? i/o interfacing ........................................................................................................................ 48 programming considerations ................................................................................................ 48 timer program examp ?e ....................................................................................................... 49 time base ....................................................................................................... 50 pulse width modulator .................................................................................. 50 pwm operation ..................................................................................................................... 50 ?+? pwm mode .................................................................................................................... 51 7+1 pwm mode .................................................................................................................... 5? pwm o?tp?t contro? ............................................................................................................. 5? pwm programming examp?e ................................................................................................ 53
rev. 1.00 4 ???? 1?? ?01? rev. 1.00 5 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu analog to digital converter ......................................................................... 53 a/d overview ........................................................................................................................ 53 a/d converter data registers C adrl ? adrh ..................................................................... 54 a/d converter contro? registers C adcr0? adcr1? acer ................................................. 54 a/d operation ....................................................................................................................... 57 a/d inp?t pins ....................................................................................................................... 58 s?mmar? of a/d conversion steps ....................................................................................... 58 programming considerations ................................................................................................ ?0 a/d transfer f ?nction ........................................................................................................... ?0 a/d programming examp?e ................................................................................................... ?1 interrupts ........................................................................................................ 63 interr?pt registers ................................................................................................................. ?3 interr?pt operation ................................................................................................................ ?5 interr?pt priorit? ..................................................................................................................... ?8 externa? interr?pt ................................................................................................................... ?8 a/d converter interr?pt ......................................................................................................... ?9 timer/event co ?nter interr?pt ............................................................................................... ?9 time base interr ?pts ............................................................................................................. ?9 interr? pt wake-?p f?nction ................................................................................................... ?9 programming considerations ................................................................................................ 70 confguration options ................................................................................... 70 application circuits ....................................................................................... 70 instruction set ................................................................................................ 71 introd?ction ........................................................................................................................... 71 instr? ction timing .................................................................................................................. 71 moving and transferring data ............................................................................................... 71 arithmetic operations ............................................................................................................ 71 logica? and rotate operations .............................................................................................. 7? branches and contro? transfer ............................................................................................. 7? bit operations ....................................................................................................................... 7? tab ?e read operations ......................................................................................................... 7? other operations ................................................................................................................... 7? instruction set summary .............................................................................. 73 tab ?e conventions ................................................................................................................. 73 instruction defnition ..................................................................................... 75 package information ..................................................................................... 85 1? -pin dip (300mi?) o?t?ine dimensions ............................................................................... 85 1? -pin nsop (150mi?) o?t?ine dimensions ........................................................................... 88 ree? dimensions ................................................................................................................... 89 carrier tape dimensions ....................................................................................................... 90
rev. 1.00 4 ???? 1?? ?01? rev. 1.00 5 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu features cpu features operating voltage: ? f sys = 4mhz: 2.2v~5.5v ? f sys =8mhz: 3.3v ~ 5.5v ? f sys =12mhz: 4.5v ~ 5.5v up to 0.33s instruction cycle with 12mhz system clock at v dd =5v oscillator types: ? external high frequency crystal -- hxt ? internal rc -- hirc power down modes and wake-up function fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components lirc oscillator function for watchdog timer all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 4-level stack bit manipulation instruction peripheral features up to 204816 program memory up to 968 data memory up to 14 bidirectional i/o lines up to 4 channel 12-bit adc 1 channel 8-bit pwm low voltage reset function watchdog timer function external interrupt input shared with an i/o line up to two 8-bit programmable timer/event counter with overfow interrupt and prescaler time-base functions programmable frequency divider - pfd package types: 16 dip/nsop
rev. 1.00 ? ???? 1?? ?01? rev. 1.00 7 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu general description the enhanced a/d mcus are a series of 8-bit high performance, risc architecture microcontrollers specifcally designed for a wide range of applications. the usual holtek microcontroller features of low power consumption, i/o fexibility, timer functions, oscillator options, power down and wake-up functions, watchdog timer and low voltage reset, combine to provide devices with a huge range of functional options while still maintaining a high level of cost effectiveness. the fully integrated system oscillator hirc, which requires no external components and which has three frequency selections, opens up a huge range of new application possibilities for these devices, some of which may include industrial control, consumer products, household appliances subsystem controllers, etc. selection table part no. rom ram i/o 8-bit t imer t ime base hirc (mhz) a/d pwm pfd stack package ht // -b -b /n t // -b -b /n block diagram

pin assignment ht 46 r 017 16 dip / nsop - a pa3 / int pa? / tc 0 pa 1 / pfd pa 0 / pfd vss pb0 / an 0 / vref pb1 / an 1 pb? / an ? pa4 / pwm / tc 1 pa5 / osc ? pa? / osc 1 pa7 vdd pb5 pb4 pb3 / an 3 1? 15 14 13 1? 11 1 0 9 1 ? 3 4 5 ? 7 8 ht 46 r 016 16 dip / nsop - a pa3 / int pa? / tc 0 pa1 / pfd pa0 / pfd vss pb0 / an 0 / vref pb1 / an 1 pb? / an ? pa4 / pwm pa5 / osc ? pa? / osc 1 pa 7 vdd pb5 pb4 pb3 / an 3 1? 15 14 13 1? 11 10 9 1 ? 3 4 5 ? 7 8
rev. 1.00 ? ???? 1?? ?01? rev. 1.00 7 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu pin description ht46r016 pin name function opt i/t o/t description pa0/pfd pa0 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p pfd ctrl0 cmos pfd o?tp?t pa1/ pfd pa1 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p pfd ctrl0 cmos pfd comp?ementar? o?tp?t pa ?/tc0 pa ? papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p tc0 tmr0c st externa? timer 0 c?ock inp?t pa3/int pa3 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p int ctrl0 st externa? interr?pt inp?t pa4/pwm pa4 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p pwm ctrl0 cmos pwm o?tp?t pa5/osc ? pa5 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p osc? co hxt osci??ator pin pa ?/osc1 pa ? papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p osc1 co hxt osci??ator pin pa7 pa7 pawk st nmos genera? p?rpose i/o. register enab?ed wake-?p pb0/an0/ vref pb0 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p an0 adcr0 an a/d channe? 0 vref adcr1 an a/d reference inp?t pb1/an1~ pb3/an3 pbn pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p ann adcr0 an a/d channe? n pb4~pb5 pbn pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p vdd vdd pwr power s?pp?? vss vss pwr gro?nd
rev. 1.00 8 ???? 1?? ?01? rev. 1.00 9 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu HT46R017 pin name function opt i/t o/t description pa0/pfd pa0 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p pfd ctrl0 cmos pfd o?tp?t pa1/ pfd pa1 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p pfd ctrl0 cmos pfd comp?ementar? o?tp?t pa ?/tc0 pa ? papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p tc0 tmr0c st externa? timer 0 c?ock inp?t pa3/int pa3 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p int ctrl0 st externa? interr?pt inp?t pa4/pwm/tc1 pa4 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p pwm ctrl0 cmos pwm o?tp?t tc1 tmr1c st externa? timer 1 c?ock inp?t pa5/osc ? pa5 papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p osc? co hxt osci??ator pin pa ?/osc1 pa ? papu pawk st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p osc1 co hxt osci??ator pin pa7 pa7 pawk st nmos genera? p?rpose i/o. register enab?ed wake-?p pb0/an0/ vref pb0 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p an0 adcr0 an a/d channe? 0 vref adcr1 an a/d reference inp?t pb1/an1~ pb3/an3 pbn pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p ann adcr0 an a/d channe? n pb4~pb5 pbn pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p vdd vdd pwr power s?pp?? vss vss pwr gro?nd note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; an: analog input hxt: high frequency crystal oscillator
rev. 1.00 8 ???? 1?? ?01? rev. 1.00 9 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature ................................................................................................... -50 c to 125c operating temperature ................................................................................................. -40 c to 85 c i oh total .................................................................................................................................. -100ma i ol total ................................................................................................................................... 100ma total power dissipation ........................................................................................................ 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c.characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating vo ?tage f sys =4mh z ?.? 5.5 v f sys =8mhz 3. 3 5.5 v f sys =1?mhz 4.5 5.5 v i dd1 operating c?rrent (hxt ? hirc) 3v no ?oad? f sys =4mhz? adc disab?e 1 ? ma 5v ?.5 5 ma i dd? operating c?rrent (hxt ? hirc) 5v no ?oad? f sys =8mhz? adc disab?e 4 8 ma i dd3 operating c?rrent (hxt ? hirc) 5v no ?oad? f sys =1?mhz? adc disab?e ? 1? ma i stb1 standb? c?rrent (lirc on) 3v no ?oad? s? stem halt 5 a 5v 10 a i stb? standb? c? rrent (lirc off) 3v no ?oad? s? stem halt 1 a 5v ? a v il1 inp? t low vo? tage for pa? pb? tcn? int (except pa7) 5v 0 1.5 v 0 0.?v dd v v ih1 inp? t high vo? tage for pa? pb? tcn? int (except pa7) 5v 3.5 5 v 0.8v dd v dd v v il? inp? t low vo? tage (pa7) 0 0.4v dd v v ih? inp? t high vo? tage (pa7) 0.9v dd v dd v i ol1 i/o sink c? rrent (pa?pb) 3v v ol =0.1v dd 4 8 ma 5v 10 ?0 ma i oh1 i/o so?rce c?rrent (pa ?pb) 3v v oh =0.9v dd -? -4 ma 5v -5 -10 ma i ol? pa7 sink c ?rrent 5v v ol =0.1v dd ? 3 ma r ph p???-high resistance (i/o) 3v ?0 ?0 100 k 5v 10 30 50 k note: the standby current (i stb1 ~i stb2 ) are measured with all i/o pins in input mode and tied to vdd.
rev. 1.00 10 ???? 1?? ?01? rev. 1.00 11 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu a.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd condition f sys s?stem c?ock ?.?~5.5v 3? 4000 khz 3. 3 ~5.5v 3? 8000 khz 4.5~5.5v 3? 1?000 khz f hirc s?stem c?ock (hirc) 3.3v/5v ta= ?5 ? c -?% 4/8 +?% mhz 5v ta= ?5 ? c -?% 1? +?% mhz 3.3v/5v ta=0~70 ? c -5% 4/8 +5% mhz 5v ta=0~70 ? c -5% 1? +5% mhz ?.?v~3.?v ta=0~70c -8% 4 +8% mhz 3.3v~5.5v ta=0~70c -8% 4/8 +8% mhz 4.5v~5.5v ta=0~70c -8% 1? +8% mhz ?.?v~3.?v ta=-40 c ~85c -1?% 4 +1?% mhz 3.3v~5.5v ta=-40 c ~85c -1?% 4/8 +1?% mhz 4.5v~5.5v ta=-40 c ~85c -1?% 1? +1?% mhz f lirc s?stem c?ock (lirc) 5v ?8.8 3? 35.? khz ?.?v~5.5v ta=-40 c ~85c 1? 3? 51.? khz t ss t s?stem start-?p timer period (wake-?p from power down mode) f sys =hxt 10?4 t sys f sys =hirc ? t tc tcn inp?t pin p??se width 0.3 s t i nt interr?pt inp?t pin p??se width 10 s t rstd s?stem reset de?a? time (power on reset) ?5 50 100 ms s?stem reset de?a? time (an? reset except power on reset) 8.3 1?.7 33.3 ms note: 1. t sys =1/f sys 2. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. adc characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions dnl a/d differentia ? non-?inearit? 3v t ad =0.5s -? +? lsb 5v inl adc integra? non-?inearit? 3v t ad =0.5s -4 +4 lsb 5v 5v i adc additiona? power cons?mption if a/d converter is used 3v 0.5 0.75 ma 5v 1.0 1.5 ma t ad a/d c?ock period ?.7v~5.5v 0.5 10 s t adc a/d conversion time (note) ?.7v~5.5v 1? - bit adc 1? t ad t on?st adc on to adc start ?.7v~5.5v ? s v ref inp? t reference vo?tage range ?.0 v dd +1 v note: adc conversion time (t ad )= n (bits adc) + 4 (sampling time), the conversion for each bit needs one adc clock(t ad ).
rev. 1.00 10 ???? 1?? ?01? rev. 1.00 11 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu lvr characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low vo ? tage reset vo?tage lvr enab ?e? ?.1v se?ected -5% t ?p. ?.1 +5% t ?p. v v lvr ? lvr enab ?e? ?.55v se?ected ?.55 v v lvr3 lvr enab ?e? 3.15v se?ected 3.15 v v lvr4 lvr enab ?e? 3.8v se?ected 3.8 v v bg bandgap reference vo ?tage with b? ffer - 3 % 1.?5 + 3 % v i lvr a dditiona? power cons?mption 3v lvr enab ?ed 30 45 a 5v ?0 90 a t bg v bg t ? rn on stab? e time ?00 s t lvr l ow vo ?tage width to reset 1?0 ?40 480 s t sreset s oftware reset width to reset 45 90 1?0 s power-on reset characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start vo ?tage to ens?re power-on reset 100 mv rr vdd v dd raising rate to ens?re power-on reset 0.035 v/ms t por minim? m time for v dd sta?s at v por to ens? re power-on reset 1 ms
rev. 1.00 1? ???? 1?? ?01? rev. 1.00 13 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. clocking and pipelining the main system clock, derived from either a crystal/resonator or rc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frstly obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.00 1? ???? 1?? ?01? rev. 1.00 13 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu
? ? ? ? ? ? ? ? ? ? instruction fetching program counter C pc during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumping to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc, the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register ht4?r01? pc9? pc8 pcl7~pcl0 ht4?r017 pc10~pc8 the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly. however, as only this low byte is available for manipulation, the jumps are limited in the present page of memory, which have 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the conte nts of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack.
rev. 1.00 14 ???? 1?? ?01? rev. 1.00 15 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu 4 device stack levels ht4?r01? ? ht4?r017 4 if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti.
rev. 1.00 14 ???? 1?? ?01? rev. 1.00 15 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu progam memory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp device offers users the fexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. structure the program memory has a capacity of 1k16 to 2k16. the program memory is addressed by the program counter and also contains data, table information and interrupt entries information. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. device capacity ht4?r01? 1k1? ht4?r017 ?k1? 3ffh 7ffh 16 bits time base interrupt timer 0 interrupt a/d interrupt external interrupt reset 18h 10h 14h 0ch 08h 04h 00h ht46r016 16 bits time base interrupt a/d interrupt timer 0 interrupt timer 1 interrupt external interrupt reset HT46R017 program memory structure
rev. 1.00 1? ???? 1?? ?01? rev. 1.00 17 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. reset vector this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. external interrupt vector this vector is used by the external interrupt. if the external interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled anthe stack is not full. the external interrupt active edg transition type, whether high to low, low to high or both is specifed in the ctrl0 register. timer/event 0/1 counter interrupt vector this internal vector is used by the timer/event counters. if a timer/event counter overflow occurs, the program will jump to its respective location and begin execution if the associated timer/event counter interrupt is enabled and the stack is not full. time base interrupt vector this internal vector is used by the internal time base. if a time base overflow occurs, the program will jump to this location and begin execution if the time base counter interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc [m] or tabrdl [m] instructions, respectively. when these instructions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the following diagram illustrates the addressing data fow of the look-up table: pc high byte last page or present page pcx~pc8 data 16 bits program memory address register tblh high byte low byte user selected register tblp register
rev. 1.00 1? ???? 1?? ?01? rev. 1.00 17 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc10 pc9 pc8 @7 @? @5 @4 @3 @? @1 @0 tabrdl [m] 1 1 1 @7 @? @5 @4 @3 @? @1 @0 table location note: pc10~pc8: current program counter bits @7~@0: table pointer tblp bits for the ht46r016, the table address location is 10 bits, i.e. from b9~b0. for the HT46R017, the table address location is 11 bits, i.e. from b10~b0. table read program example: tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer C note that this address ; is referenced mov tblp, a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempreg1 data at prog.memory address 306h ; transferred to to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 data at prog.memory address 305h ; transferred to tempreg2 and tblh in this example the ; data 1ah is transferred to tempreg1 and data 0fh ; to register tempreg2 the value 00h will be ; transferred to the high byte register tblh : : org 300h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 18 ???? 1?? ?01? rev. 1.00 19 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu data memory the data memory is a volatile area 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. device capacity ht4?r01? ?48 ht4?r017 9?8 the two sections of data memory, the special purpose and general purpose data memory are located at consecutive locations. all are implemented in ram and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. the start address of the data memory for all devices is the address "00h". all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user program for both read and write operations. by using the"set [m].i" and "clr [m].i" instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. 01h 3fh 9fh 7fh iar0 ht46r016 mp0 00h 40h special purpose registers general purpose registers 64 bytes iar0 HT46R017 mp0 96 bytes data memory structure note: most of the data memory bits can be directly manipulated using the "set [m].i" and "clr [m].i" with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers.
rev. 1.00 18 ???? 1?? ?01? rev. 1.00 19 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value "00h". adcr1 adcr1 acer acer pfdctrl ctrl1 lvrc adcr0 adcr0 adrh adrl pwm intc1 ctrl0 pawk papu pac pa pbpu pbc pb tmr0c tmr0 intc0 status wdtc tblh tblp pcl acc mp1 iar1 mp0 iar0 ht46r016 HT46R017 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 3dh 3eh 3fh pfdctrl ctrl1 lvrc adrh adrl pwm intc1 ctrl0 pawk papu pac pa pbpu pbc pb tmr0c tmr0 tmr1c tmr1 intc0 status wdtc tblh tblp pcl acc mp1 iar1 mp0 iar0 special purpose data memory
rev. 1.00 ?0 ???? 1?? ?01? rev. 1.00 ?1 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu special function register to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory begins at the address "00h". any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of "00h". indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointer, mp0 or mp1. acting as a pair, iar0 with mp0 and iar1 with mp1 can together access data from the data memory. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data . section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code. section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown a bove, no reference is made to specifc data memory addresses.
rev. 1.00 ?0 ???? 1?? ?01? rev. 1.00 ?1 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however as the register is only 8-bit wide only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller . with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. note that bits 0~3 of the status register are both readable and writeable bits.
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?3 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r/w r/w r/w r/w r/w r/w por 0 0 x x x x x ?nknown bit 7~6 unimplemented, read as 0 bit 5 to: watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrowing does not take place during a subtraction operation c is also affected by a rotate through carry instruction
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?3 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu input/output ports and control registers within the area of special function registers, the port pa, pb, etc data i/o registers and their associated control register pac, pbc, etc play a prominent role. these registers are mapped to specific addresses within the data memory as shown in the data memory table. the data i/o registers, are used to transfer the appropriate output or input data on the port. the control registers specifes which pins of the port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one fexible feature of these registers is the ability to directly program single bits using the "set [m].i" and "clr [m].i" instructions. the ability to change i/o pins from output to input and vice versa by manipulating specifc bits of the i/o control registers during normal program operation is a useful feature of these devices. system control registers C ctrl0, ctrl1 these registers are used to provide control over various internal functions. some of these include the pfd control, pwm control, certain system clock options, external interrupt edge trigger type, watchdog timer enable function, time base function division ratio. ctrl0 register bit 7 6 5 4 3 2 1 0 name integ1 integ0 tbsel1 tbsel0 pwmsel pwmc0 r/w r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 0 bit 7~6 integ1, integ0: external interrupt edge type 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 5~4 tbsel1, tbsel0: time base period selection 00: 2 10 /f tp 01: 2 11 /f tp 10: 2 12 /f tp 11: 2 13 /f tp bit 3~2 unimplemented, read as "0" bit 1 pwmsel: pwm type selection 0: (6+2) mode 1: (7+1) mode bit 0 pwmc0: i/o or pwm selection 0: i/o function 1: pwm function
rev. 1.00 ?4 ???? 1?? ?01? rev. 1.00 ?5 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu ctrl1 register bit 7 6 5 4 3 2 1 0 name lvrf lrf wrf r/w r/w r/w r/w por x 0 0 x ?nknown bit 7~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. wake-up function register C pawk when the microcontroller enters the sleep mode, various methods exist to wake the device up and continue with normal operation. one method is to allow a falling edge on the i/o pins to have a wake-up function. this register is used to select which port a i/o pins are used to have this wake-up function. pull-high registers C papu, pbpu the i/o pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates the need for external pull-high resistors. this register selects which i/o pins are connected to internal pull-high resistors.
rev. 1.00 ?4 ???? 1?? ?01? rev. 1.00 ?5 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving . oscillator selections and operation are selected through a combination of confguration options and registers. system oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base functions. external oscillators requiring some external components as well as a two fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. type name freq. pins externa? cr?sta? hxt 400 k hz~1?mhz osc1/osc? interna? high speed rc hirc 4? 8 or 1?mhz interna? low speed rc lirc 3? k hz oscillator types system clock confgurations there are two system oscillators. these two system oscillators are the external crystal/ceramic oscillator C hxt, and the internal rc oscillator C hirc. the low speed oscillator is the internal 32khz (v dd =5v) oscillator C lirc. external crystal/resonator oscillator C hxt the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation. however, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. crystal oscillator c1 and c2 values crystal frequency c1 c2 1?mhz 8pf 10pf 8mhz 8pf 10pf 4mhz 8pf 10pf 1mhz 100pf 100pf note: c1 and c? va??es are for g?idance on?? . crystal recommended capacitor values
? ? ?? crystal/resonator oscillator C hxt
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?7 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pa5 and pa6 are free for use as normal i/o pins. internal rc oscillator pa5/osc2 pa6/osc1 note: pa5/pa6 used as normal i/os internal rc oscillator C hirc internal low speed oscillator C lirc the lirc is a fully self-contained free running on-chip rc oscillator with a typical frequency of 32khz at 5v requiring no external components. when the device enters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active.
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?7 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu power down mode and wake-up entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruction in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt function is enabled. the i/o ports will maintain their present condition. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. the watchdog timer will continue to run when in the power down mode and thus will consume some power since the watchdog timer is enabled and the clock source is derived from the lirc oscillator.
rev. 1.00 ?8 ???? 1?? ?01? rev. 1.00 ?9 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external falling edge on pa0~pa7 a system interrupt a wdt overfow if the system is woken up by power-on reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf fags. the pdf fag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. pins pa0 to pa7 can be setup via the pawk register to permit a negative transition on the pin to wake-up the system. when a pa0 to pa7 pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which wake-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set to 1 before entering the power down mode, then any future interrupt requests will not generate a wake-up function of the related interrupt will be ignored. no matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time delay before normal program execution resumes. consult the table for the related time. wake-up source oscillator type hirc hxt power-on/lvr reset t rsdt +t sst? t rsdt +t sst? pa0~pa7 i/o port t sst1 t sst? interr?pt wdt overfow wake-up delay time note: 1. t rstd (reset delay time), t sys (system clock) 2. t rstd is power-on delay, typical time=50ms 3. t sst1 =2t sys 4. t sst2 =1024t sys
rev. 1.00 ?8 ???? 1?? ?01? rev. 1.00 ?9 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f s , which is in turn supplied by the lirc oscillator. the lirc internal oscillator has an approximate period of 32 khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this register together with the corresponding configuration option control the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0: wdt function software control 10101: disabled 01010: enabled other: reset mcu when these bits are changed by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl1 register will be set to 1. bit 2~0 ws2~ws0: wdt time-out period selection 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s
rev. 1.00 30 ???? 1?? ?01? rev. 1.00 31 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu ctrl1 register bit 7 6 5 4 3 2 1 0 name lvrf lrf wrf r/w r/w r/w r/w por x 0 0 x ?nknown bit 7~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag describe elsewhere. bit 1 lrf: lvr control register software reset fag describe elsewhere. bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. with regard to the watchdog timer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to offer additional enable/disable and reset control of the watchdog timer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values by the environmental noise, except 01010b and 10101b, it will reset the device after 2~3 lirc clock cycles. after power on these bits will have the value of 01010b. wdt c onfguration option we4 ~ we0 bits wdt function a pp?ication program enab?ed 10101b d isab?e 01010b e nab?e an? other va??e r eset mcu watchdog timer enable/disable control
rev. 1.00 30 ???? 1?? ?01? rev. 1.00 31 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the power down mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single clr wdt instruction to clear the wdt. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdtinstr?ction 8-stage divider wdt presca?er we4~we0 bits wdtc register reset mcu lirc f s f lirc f s /? 8 8-to-1 mux clr ws?~ws0 (f s /? 8 ~ f s /? 18 ) wdt time-o?t (? 8 /f s ~ ? 18 /f s ) watchdog timer
rev. 1.00 3? ???? 1?? ?01? rev. 1.00 33 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters . the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defned state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. the microcontroller has an internal rc reset function, due to unstable power on conditions. this time delay created by the rc network ensures the state of the por remains low for an extended period while the power supply stabilizes. during this time, normal operation of the microcontroller is inhibited. after the state of the por reaches a certain voltage value, the reset delay time t por is invoked to provide an extra delay time after which the microcontroller can begin normal operation. vdd power-on reset sst time-out t rstd power-on reset timing chart
rev. 1.00 3? ???? 1?? ?01? rev. 1.00 33 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the ctrl1 register will also be set to 1. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specified by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the lvs bits in the lvrc register. if the lvs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the lvr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl1 register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. low voltage reset timing chart lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs ? lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0: lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.55v any other values: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value.
rev. 1.00 34 ???? 1?? ?01? rev. 1.00 35 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu ctrl1 register bit 7 6 5 4 3 2 1 0 name lvrf lrf wrf r/w r/w r/w r/w por x 0 0 "x": ?nknown bit 7~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere. watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware power-on reset except that the watchdog time-out fag to will be set to "1". wdt time-out reset during normal operation timing chart watchdog time-out reset during power down mode the watchdog time-out reset during power down mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out reset during power down mode timing chart note: the t sst is 2 clock cycles for hirc. the t sst is 1024 clock cycles for hxt.
rev. 1.00 34 ???? 1?? ?01? rev. 1.00 35 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down mode function or watchdog timer. the reset fags are shown in the table: to pdf reset conditions 0 0 power-on reset ? ? lvr reset d ? ring normal mode operation 1 ? wdt time-o ?t reset d? ring normal mode operation 1 1 wdt time-o ?t reset d?ring power down mode operation ? ?nchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program co?nter reset to zero interr?pts a?? interr?pts wi?? be disab?ed presca?er ? divider c?eared wdt c?ear after reset? wdt begins co?nting timer/event co ?nter timer co ?nter wi?? be t? rned off inp?t/o?tp?t ports i/o ports wi?? be set?p as inp?ts stack pointer stack pointer wi?? point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller internal registers.
rev. 1.00 3? ???? 1?? ?01? rev. 1.00 37 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu register ht46r016 HT46R017 power on reset lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (halt)* mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? acc xxxx xxxx ???? ???? ???? ???? ???? ???? tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? wdtc 0101 0011 0101 0011 0101 0011 ???? ???? status --00 xxxx --?? ???? --1? ???? --11 ???? intc0 -000 0000 -000 0000 -000 0000 -??? ???? intc1 --00 --00 --00 --00 --00 --00 --?? --?? intc1 ---0 ---0 ---0 ---0 ---0 ---0 --- ? --- ? tmr0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? tmr0c 00-0 1000 00-0 1000 00-0 1000 ??-? ???? tmr1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? tmr1c 00-0 1--- 00-0 1--- 00-0 1--- ??-? ?--- pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? papu -000 0000 -000 0000 -000 0000 -??? ???? pawk 0000 0000 0000 0000 0000 0000 ???? ???? pb --11 1111 --11 1111 --11 1111 --?? ???? pbc --11 1111 --11 1111 --11 1111 --?? ???? pbpu --00 0000 --00 0000 --00 0000 --?? ???? ctrl0 1000 --00 1000 --00 1000 --00 ???? --?? ctrl1 ---- -x00 ---- - ??? ---- - ??? ---- - ??? pwm xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- ???? ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=0) ---- xxxx ---- xxxx ---- xxxx ---- ???? adrh (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adcr0 0110 --00 0110 --00 0110 --00 ???? --?? adcr1 -000 -000 -000 -000 -000 -000 -??? -??? acer ---- 0000 ---- 0000 ---- 0000 ---- ???? pfdctrl ---- --00 ---- --00 ---- --00 ---- -- ?? pfdctrl ---- -000 ---- -000 ---- -000 ---- - ??? lvrc 0101 0101 0101 0101 0101 0101 ???? ???? note: - not implement u means unchanged x means unknown
rev. 1.00 3? ???? 1?? ?01? rev. 1.00 37 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. most pins can have either an input or output designation under user program control. additionally, as there are pull-high resistors and wake-up software confgurations, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu, pbpu located in the data memory. the pull-high resistors are implemented using weak pmos transistors. note that pin pa7 does not have a pull-high resistor selection. port a wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the pa0~pa7 pins from high to low. after a halt instruction forces the microcontroller into entering the idle/sleep mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that pins pa0 to pa7 can be selected individually to have this wake-up feature using an internal register known as pawk, located in the data memory. pawk, pac, papu, pbc, pbpu register register name bit 7 6 5 4 3 2 1 0 pawk pawk7 pawk ? pawk5 pawk4 pawk3 pawk ? pawk1 pawk0 pac pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 papu papu ? papu5 papu4 papu3 papu ? papu1 papu0 pbc pbc5 pbc4 pbc3 pbc? pbc1 pbc0 pbpu pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 unimplemented, read as 0 pawkn: pa wake-up function enable 0: disable 1: enable pacn/pbcn: i/o type selection 0: output 1: input papun/pbpun: pull-high function enable 0: disable 1: enable
rev. 1.00 38 ???? 1?? ?01? rev. 1.00 39 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu i/o port control registers each port has its own control register, known as pac, pbc which controls the input/output configuration. with this control register, each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by confguration options while for others the function is set by application program control. external interrupt input the external interrupt pin, int, is pin-shared with an i/o pin. to use the pin as an external interrupt input the correct bits in the intc0 register must be programmed. the pin must also be setup as an input by setting the pac3 bit in the port control register. a pull-high resistor can also be selected via the appropriate port pull-high resistor register. note that even if the pin is setup as an external interrupt input the i/o function still remains. external timer/event counter input the timer/event counter pins, tc0 and tc1 are pin-shared with i/o pins. for these shared pins to be used as timer/event counter inputs, the timer/event counter must be confgured to be in the event counter or pulse width capture mode. this is achieved by setting the appropriate bits in the timer/event counter control register. the pins must also be setup as inputs by setting the appropriate bit in the port control register. pull-high resistor options can also be selected using the port pull-high resistor registers. note that even if the pin is setup as an external timer input the i/o function still remains. pfd output the pfd complementary output pair is pin-shared with i/o pins. the output function of these pins is chosen using the pfdctrl register. note that the corresponding bit of the port control register, must setup the pin as an output to enable the pfd output. if the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pfd function has been selected. pwm outputs the pwm function output is pin-shared with an i/o pin. the pwm output function is chosen using the ctrl0 register. note that the corresponding bit of the port control registers, for the output pin, must setup the pin as an output to enable the pwm output. if the pin is setup as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pwm register has enabled the pwm function.
rev. 1.00 38 ???? 1?? ?01? rev. 1.00 39 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu a/d inputs each device in this series has four inputs to the a/d converter. all of these analog inputs are pin-shared with i/o pins. if these pins are to be used as a/d inputs and not as i/o pins, then the corresponding acen bits in the a/d converter channel enable control register, acer, must be properly setup. if chosen as i/o pins, then full pull-high resistor confgurations remain. however, if used as a/d inputs, then any pull-high resistor confgurations associated with these pins will be automatically disconnected. i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins.

??? ?? ? ? ? generic input/output ports

? ? ? pa7 nmos input/output port
rev. 1.00 40 ???? 1?? ?01? rev. 1.00 41 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure programming considerations within the user program, one of the things frst to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. system clock port data read from port write to port t1 t2 t3 t4 t1 t2 t3 t4 read modify write timing pins pa0 to pa7 each have a wake-up functions, selected via the pawk register. when the device is in the idle/sleep mode, various methods are available to wake the device up. one of these is a high to low transition of any of the these pins. single or multiple pins on port a can be setup to have this function.
rev. 1.00 40 ???? 1?? ?01? rev. 1.00 41 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu timer/event counter the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices contain from one to two count-up timers of 8-bit capacity. as the timers have three different operating modes, they can be confgured to operate as a general timer, an external event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry on giving added range to the timers. there are two types of registers related to the timer/event counters. the frst is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defnes the timer options and determines how the timer is to be used. the device can have the timer clock confgured to come from the internal clock source. in addition, the timer clock source can also be confgured to come from an external timer pin. confguring the timer/event counter input clock source the timer/event counter clock source can originate from an internal clock or an external pin. the internal clock source is used when the timer is in the timer mode or in the pulse width capture mode. for timer/event counter 0, this internal clock source is frst divided by a prescaler, the division ratio of which is conditioned by the timer control register bits t0psc0~t0psc2. for timer/event counter 0, the internal clock source is derived from f sys while the internal clock source is derived from the instruction clock cycle, f sys /4, for timer/event counter 1. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tcn. depending upon the condition of the tneg bit, each high to low, or low to high transition on the external timer pin will increment the counter by one.

?
? ? ? ?
? ? ?
?
- ? ? ? ? ? ? ? ? ? ? clock structure

? ?? ? ? ? ? -
? ? ? 8-bit timer/event counter 0 structure

? ?
? ?
?

? ? ? - ? 8-bit timer/event counter 1 structure
rev. 1.00 4? ???? 1?? ?01? rev. 1.00 43 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu pfd0 pfd1 pfdcs mux 0 1 pfd output timer registers C tmr0, tmr1 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. these registers are known as tmr0 and tmr1. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh at which point the timer overfows and an internal interrupt signal is generated. then the timer value will be reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh, all the preload registers must first be cleared to zero. it should be noted that after power-on, the preload registers will be in an unknown condition. note that if the timer/event counter is in an off condition and data is written to its preload register, this data will be immediately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overfow occurs. timer control registers C tmr0c, tmr1c the fexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. the timer control register is known as tmrnc. it is the timer control register together with its corresponding timer registers that control the full operation of the timer/event counter. before the timer can be used, it is essential that the timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the timer control register, which are known as the bit pair tnm1/tnm0, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run. clearing the bit stops the counter. bits 0~2 of the timer control register 0 determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tneg.
rev. 1.00 4? ???? 1?? ?01? rev. 1.00 43 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu tmr0c register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0on t0eg t0psc? t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 bit 7,6 t0m1, t0m0: timer 0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 unimplemented, read as 0 bit 4 t0on: timer/event counter counting enable 0: disable 1: enable bit 3 t0eg: event counter active edge selection 1: count on falling edge 0: count on rising edge pulse width capture active edge selection 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge bit 2~0 t0psc2, t0psc1, t0psc0: timer prescaler rate selection timer internal clock 000: f tp 001: f tp /2 010: f tp /4 011: f tp /8 100: f tp /16 101: f tp /32 110: f tp /64 111: f tp /128 tmr1c register bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1on t1eg r/w r/w r/w r/w r/w por 0 0 0 1 bit 7, 6 t1m1, t1m0: timer 1 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 unimplemented, read as 0 bit 4 t1on: timer/event counter counting enable 0: disable 1: enable bit 3 t1eg: event counter active edge selection 1: count on falling edge 0: count on rising edge pulse width capture active edge selection 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge bit 2~0 unimplemented, read as 0
rev. 1.00 44 ???? 1?? ?01? rev. 1.00 45 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu timer mode in this mode, the timer/event counter can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the timer/event counter overfows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. bit7 bit6 1 0 control register operating mode select bits for the timer mode in this mode the internal clock is used as the timer clock. the timer input clock source is f sys or f sys /4. however, this timer clock source is further divided by a prescaler, the value of which is determined by the bits t0psc2~t0psc0 in the timer control register. the timer-on bit, tnon must be enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overflows, an interrupt sigal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overfow condition and corresponding internal interrupts are two of the wake-up sources. however, the internal interrupts can be disabled by ensuring that the tne bits of the intc0 register are reset to zero.
timer mode timing chart event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tcn pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. bit7 bit6 0 1 control register operating mode select bits for the timer mode in this mode, the external timer tcn, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tneg, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the tneg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control re gister. it is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is confgured to operate as an event counter input pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode. the second is to ensure that the port control register confgures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input tcn pin. as a result when the timer overfows it will generate a timer interrupt and corresponding wake-up source.
rev. 1.00 44 ???? 1?? ?01? rev. 1.00 45 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu
event counter mode timing chart (tneg=1) pulse width capture mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. bit7 bit6 1 1 control register operating mode select bits for the pulse width capture mode in this mode the internal clock, f sys or f sys /4 is used as the internal clock for the 8-bit timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits t0psc2~t0psc0, which tnon, which is bit 2~0 of the timer control register, can be set high to enabl the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit tneg, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tcn pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width capture until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, it is reset to zero. as the tcn pin is shared with an i/o pin, to ensure that the pin is confgured to operate as a pulse width capture pin, two things have to be implemented. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width capture mode, the second is to ensure that the port control register confgure the pin as an input.
rev. 1.00 4? ???? 1?? ?01? rev. 1.00 47 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu

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? ? ? ? ? ? ? ?? - pulse width capture mode timing chart (tneg=0) prescaler bits t0psc0~t0psc2 of the tmrnc register can be used to defne a division ratio for the internal clock source of the timer/event counter enabling longer time-out periods to be setup. pfd function the programmable frequency divider provides a means of producing a variable frequency output suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency generator. the timer/event counter overflow signal is the clock source for the pfd function, which is controlled by pfdcs bit in pfdctrl. for applicable devices the clock source can come from either timer/event counter 0 or timer/event counter 1. the output frequency is controlled by loading the required values into the timer prescaler and timer registers to give the required division ratio. the counter will begin to count-up from this preload register value until full, at which point an overfow signal is generated, causing both the pfd outputs to change state. then the counter will be automatically reloaded with the preload register value and continue counting-up. if the pfdctrl register has selected the pfd function, then for pfd output to operate, it is essential for the port a control register pac to setup the pfd pins as outputs. the pa0 data bit must be set high to activate the pfd function if only the pfd function is enabled. however, if the pfd and pfd functions both are enabled, the pa0 and pa1 data bits must be set high to activate the pfd and pfd complementary outputs. the output data bits can be used as the on/off control bit for the pfd outputs. note that the pfd outputs will all be low if the output data bit is cleared to zero. using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated.
rev. 1.00 4? ???? 1?? ?01? rev. 1.00 47 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu pfdctrl register ht46r016 bit 7 6 5 4 3 2 1 0 name pfden1 pfden0 r/w r/w r/w por 0 0 HT46R017 bit 7 6 5 4 3 2 1 0 name pfdcs pfden1 pfden0 r/w r/w r/w r/w por 0 0 0 bit7~3 : unused, read as 0. bit2 pfdcs: pfd clock source selection 0: timer 0 1: timer 1 bit1~0 pfden1~pfden0: pfd/ pfd enable control 00: both disabled 01: reserved 10: pfd enabled 11: pfd and pfd both enabled

pfd function C complementary outputs

pfd function C single output
rev. 1.00 48 ???? 1?? ?01? rev. 1.00 49 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be confgured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode selects bits in the timer/event counter control register, either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is confgured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoiderrors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is frst loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register. when the timer/event counter overfows, its corresponding interrupt request fag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt request fag should frst be set high before issuing the halt instruction to enter the power down mode .
rev. 1.00 48 ???? 1?? ?01? rev. 1.00 49 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu timer program example the program shows how the timer/event counter registers are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. timer programming example org 04h ; external interrupt vector org 08h ; timer counter 0 interrupt vector jmp tmr0int ; jump here when timer 0 overfows : : org 20h ; main program : : ; internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : : begin: ; setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a : : set tmr0c.4 ; start timer 0 : :
rev. 1.00 50 ???? 1?? ?01? rev. 1.00 51 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu time base the device includes a time base function which is used to generate a regular time interval signal. the time base time interval magnitude is determined using an internal 13 stage counter sets the division ratio of the clock source. this division ratio is controlled by both the tbsel0 and tbsel1 bits in the ctrl0 register. the clock source is derived from the system clock f sys . when the time base time-out condition occurs, a time base interrupt signal will be generated. it should be noted that as the time base clock source is the same as the timer/event counter clock source, care should be taken when programming. pulse width modulator every device includes an 8-bit pwm function. useful for such applications such as motor speed control, the pwm function provides an output with a fxed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register .

pwm block diagram device channels mode pins registers ht4?r01?/017 1 ?+? 7+1 pa4 pwm pwm operation a single register, known as pwm and located in the data memory is assigned to each pulse width modulator channel. it is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be place d. to increase the pwm modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. the required mode and the on/off control for each pwm channel is selected u sing the ctrl0 register. note that when using the pwm, it is only necessary to write the required value into the pwmn register and select the required mode setup and on/off control using the ctrl0 register, the subdivision of the wave form into its sub-modulation cycles is implemented automatically within the microcontroller hardware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generatio n of higher pwm frequencies which allow a wider range of applications to be served. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is the system clock, f sys , and as th e pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however, when in the 7+1 mode of operation the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64.
rev. 1.00 50 ???? 1?? ?01? rev. 1.00 51 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu pwm modulation pwm cycle frequency pwm cycle duty f sys /?4 for (?+?) bits mode f sys /1?8 for (7+1) bits mode f sys /?5? [pwm]/?5? 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0~modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit 2~bit 7 is denoted here as the dc value. the second group which consists of bit 0~bit 1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) dc dc(duty cycle) mod??ation c?c?e i (i=0~3) iac dc/?4 6+2 mode modulation cycle values the following diagram illustrates the waveforms associated with the 6+2 mode of pwm operation. it is important to note how the single pwm cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the ac value is related to the pwm value.

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6+2 pwm mode pwm register for 6+2 mode
rev. 1.00 5? ???? 1?? ?01? rev. 1.00 53 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub-cycles known as modulation cycle 0~modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit 1~bit 7 is denoted here as the dc value. the second group which consists of bit 0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac(0~1) dc (duty cycle) mod??ation c?c?e i (i=0~1) i=ac dc/1?8 the following diagram illustrates the waveforms associated with the 7+1 mode pwm operation. it is important to note how the single pwm cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the ac value is related to the pwm value.

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7+1 pwm mode pwm register for 7+1 mode pwm output control the pwm outputs are pin-shared with the i/o pins pa4. to operate as a pwm output and not as an i/o pin, the correct bits must be set in the ctrl0 register. a zero value must also be written to the corresponding bit in the i/o port control register pac.4 to ensure that the corresponding pwm output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm value has been written into the pwmn register, writing a high value to the corresponding bit in the output data register pa.4 will enable the pwm data to appear on the pin. writing a zero value will disable the pwm output function and force the output low. in this way, the port data output registers can be used as an on/off control for the pwm function. note that if the ctrl0 register has selected the pwm function, but a high value has been written to its corresponding bit in the pac control register to confgure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options.
rev. 1.00 5? ???? 1?? ?01? rev. 1.00 53 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu pwm programming example the following sample program shows how the pwm output is setup and controlled. mov a,64h ; setup pwm value of decimal 100 mov pwm,a set ctrl0.1 ; select the 7+1 pwm mode set ctrl0.0 ; select pin pa4 to have a pwm function clr pac.4 ; setup pin pa4 as an output set pa.4 ; enable the pwm output : : clr pa.4 ; disable the pwm output_ pin pa4 forced low analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a 4-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels conversion bits input pins ht4?r01?/017 4 1? pa0~pa3 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers.

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? ? ? ? ? ?? ? a/d converter structure
rev. 1.00 54 ???? 1?? ?01? rev. 1.00 55 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu register name bit 7 6 5 4 3 2 1 0 adrl (adrfs=0) d3 d? d1 d0 adrl (adrfs=1) d7 d? d5 d4 d3 d? d1 d0 adrh (adrfs=0) d11 d10 d9 d8 d7 d? d5 d4 adrh (adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff acs4 acs1 acs0 adcr1 vbgen adrfs arefs adck? adck1 adck0 acer ace3 ace? ace1 ace0 a/d converter register list a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter, they require two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d? d5 d4 d3 d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d? d5 d4 d3 d? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acer to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 and acer are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs1~acs0 bits together with the acs4 bit in the adcr0 register defne the channel number. as the device contains only one actual analog to digital converter circuit, each of the individual 4 analog inputs must be routed to the converter. it is the function of the acs1, acs0 and acs4 bits in the adcr register to determine which analog channel input pin or the internal bandgap reference voltage is actually connected to the internal a/d converter. the acen bits contained in the acer register that determine which pins on pb0~pb3 are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if the acen bit has a value of 1, then the corresponding pin, namely one of the an0~an3 analog inputs, will be set as analog inputs. once an i/o pin is selected as an analog input, the i/o function and pull-high resistor on this pin will automatically be disabled. if the acen bit is set to zero, then the corresponding pin will be setup as a normal i/o pin.
rev. 1.00 54 ???? 1?? ?01? rev. 1.00 55 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff acs4 acs1 acs0 r/w r/w r r/w r/w r/w r/w por 0 1 1 0 0 0 bit 7 start: start the a/d conversion 010: start the a/d conversion 01: reset the a/d converter and set eocb to 1 bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress bit 5 adoff: a/d module power on/off control bit 0: a/d module power on 1: a/d module power off bit 4 acs4: a/d channel selection 0: external a/d channel 1: internal bandgap reference voltage this bit enables internal bandgap reference voltage to be connected to the a/d converter. the vbgen bit must frst have been set to enable the bandgap reference voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap reference voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 3~2 unimplemented, read as 0 bit 1~0 acs1~acs0: a/d channel selection (when acs4 is 0) 00: an0 01: an1 10: an2 11: an3
rev. 1.00 5? ???? 1?? ?01? rev. 1.00 57 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu adcr1 register bit 7 6 5 4 3 2 1 0 name vbgen adrfs arefs adck? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 vbgen: internal bandgap reference voltage enable control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when bandgap reference voltage is switched on for use by the a/d converter, a time period, t bg , should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 adrfs: a/d converter data format control 0: a/d converter data msb is adrh bit7, lsb is adrl bit4 1: a/d converter data msb is adrh bit3, lsb is adrl bit0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d converter data register section. bit 4 arefs: a/d converter reference voltage selection 0: internal a/d converter power 1: external vref pin this bit is used to select the reference voltage for the a/d converter. if this bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if this bit is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as 0 bit 2~0 adck2~adck0: select a/d converter clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned, cannot be used acer register bit 7 6 5 4 3 2 1 0 name ace3 ace? ace1 ace0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~0 acen: defne the analog input n confguration (a/d input or not) 0: i/o or other pin-shared function 1: a/d input (ann input)
rev. 1.00 5? ???? 1?? ?01? rev. 1.00 57 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu a/d operation the start bit in the register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set to 1 and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter . the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , is frst divided by a division ratio, the value of which is determined by the adck2~adck0 bits in the adcr1 register. controlling the power on/off function of the a/d converter circuitry is implemented using the value of the adoff bit. although the a/d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t ad , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 8mhz, the adck2~adck0 bits should not be set to 000b or 001b. doing so will give a/d clock periods that are less than the minimum a/d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d converter clock period (t ad ) adck2~ adck0 =000 (f sys ) adck2~ adck0 =001 (f sys /2) adck2~ adck0 =010 (f sys /4) adck2~ adck0 =011 (f sys /8) adck2~ adck0 =100(f sys /16) adck2~ adck0 =101(f sys /32) adck2~ adck0 =110(f sys /64) adck2~ adck0 =111 1mhz 1s 2s 4s 8s 16s* 32s* 64s* undefned ?mhz 500ns 1s 2s 4s 8s 16s* 32s* undefned 4mhz 250ns* 500ns 1s 2s 4s 8s 16s* undefned 8mhz 125ns* 250ns* 500ns 1s 2s 4s 8s undefned 1?mhz 83ns* 167ns* 333ns* ??7ns 1.33s 2.67s 5.33s undefned a/d clock period examples
rev. 1.00 58 ???? 1?? ?01? rev. 1.00 59 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port b. bits ace3~ace0 in the acer register, determine whether the input pins are setup as normal input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to frst setup the a/d pin as an input in the i/o port control registers to enable the a/d input as when the ace3~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref.
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a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the register. step 2 select which pins are to be used as a/d inputs and confgure them as a/d input pins by correctly programming the ace3~ace0 bits in the acer register. step 3 enable the a/d by clearing the adoff bit in the adcr0 register to zero. step 4 select which channel is to be connected to the internal a/d converter by correctly programming the acs4 and acs1~acs0 bits which are also contained in the adcr0 register. step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, the intc0 interrupt control register must be set to 1, the a/d converter interrupt bit, ade, must also be set to 1.
rev. 1.00 58 ???? 1?? ?01? rev. 1.00 59 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr0 register from "0" to "1" and then to "0" again. note that this bit should have been originally set to "0". step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter function is fully under the control of the application program as there are no confguration options associ ated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period.
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rev. 1.00 ?0 ???? 1?? ?01? rev. 1.00 ?1 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu programming considerations when programming, special attention must be given to the ace3~ace0 bits in the register. if these bits are all cleared to zero, no external pins will be selected for use as a/d input pins allowing the pins to be used as normal i/o pins. setting the adoff bit high has the ability to power down the internal a/d circuitry, which may be an important consideration in power sensitive applications. a/d transfer function as the device contains a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd voltage, this gives a single bit analog input value of v dd /4096. the diagram shows the ideal transfer function between the analog input value and the digitised output alue for the a/d converter. note that to reduce the quantisation error, a 0.5lsb offset is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5lsb below where they would change without the offset, and the last full scale digitized value will change at a point 1.5lsb below the v dd level.

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rev. 1.00 ?0 ???? 1?? ?01? rev. 1.00 ?1 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acer to confgure pins an0~an3 mov acer,a mov a, 00h mov adcr0,a ; enable and connect an0 channel to a/d converter : : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?3 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acer to confgure pins an0~an3 mov acer,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a, acc_stack ; restore acc from user defned memory reti note: to power off adc module, it is necessary to set adonb as 1.
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?3 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or time base require microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contain one external interrupt and up to four internal interrupts. the external interrupt is controlled by the action of the external interrupt pin, while the internal interrupt is controlled by the timer/event counters, time base overfows and an end of a/d conversion. interrupt registers overall interrupt control, which means interrupt enabling and request flag setting, is controlled by using two registers, intc0 and intc1. by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request fag will be set by the microcontroller. the global enable fag cleared to zero will disable all interrupts. ht46r016 intc0 register bit 7 6 5 4 3 2 1 0 name adf t0f intf ade t0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 adf: a/d conversion interrupt request fag 0: inactive 1: active bit 5 t0f: timer/event counter 0 interrupt request fag 0: inactive 1: active bit 4 intf: external interrupt request fag 0: inactive 1: active bit 3 ade: a/d conversion interrupt enable 0: disable 1: enable bit 2 t0e: timer/event counter 0 interrupt enable 0: disable 1: enable bit 1 inte: external interrupt enable 0: disable 1: enable bit 0 emi: master interrupt global enable 0: disable 1: enable
rev. 1.00 ?4 ???? 1?? ?01? rev. 1.00 ?5 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu intc1 register bit 7 6 5 4 3 2 1 0 name tbf tbe r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as "0" bit 6 tbf: time base event interrupt request fag 0: inactive 1: active bit 3~1 unimplemented, read as 0 bit 0 tbe: time base event interrupt enable 0: disable 1: enable HT46R017 intc0 register bit 7 6 5 4 3 2 1 0 name t1f t0f intf t1e t0e intf emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 t1f: timer/event counter 1 interrupt request fag 0: inactive 1: active bit 5 t0f: timer/event counter 0 interrupt request fag 0: inactive 1: active bit 4 intf: external interrupt request fag 0: inactive 1: active bit 3 t1e: timer/event counter 1 interrupt enable 0: disable 1: enable bit 2 t0e: timer/event counter 0 interrupt enable 0: disable 1: enable bit 1 intf: external interrupt enable 0: disable 1: enable bit 0 emi: master interrupt global enable 0: disable 1: enable
rev. 1.00 ?4 ???? 1?? ?01? rev. 1.00 ?5 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu intc1 register bit 7 6 5 4 3 2 1 0 name tbf adf tbe ade r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 tbf: time base event interrupt request fag 0: inactive 1: active bit 4 adf: a/d conversion interrupt request fag 0: inactive 1: active bit 3~2 unimplemented, read as 0 bit 1 tbe: time base event interrupt enable 0: disable 1: enable bit 0 ade: a/d conversion interrupt enable 0: disable 1: enable interrupt operation a timer/event counter overfow, a time base event, an end of a/d conversion or an active edge on the external interrupt pin will all generate an interrupt request by setting their corresponding request fag, if their appropriate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.
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rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?7 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu
? ? ? ? ? ? ? - - - ? ? ? ? ? ? ? ? ? ? ? ? ? ? interrupt structure C HT46R017 once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. when an interrupt request is generated it takes 2 or 3 instruction cycles before the program jumps to the interrupt vector. if the device is in the sleep or idle mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector .
rev. 1.00 ?? ???? 1?? ?01? rev. 1.00 ?7 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu wait for ? ~ 3 instr?ction c?c?es main program isr entr? enab?e bit set ? main program reti ( it wi?? set emi a?tomatica??? ) a?tomatica??? disab?e interr?pt c?ear emi & req?est f?ag interr?pt req?est or interr?pt f?ag set b? instr?ction n y interrupt flow
rev. 1.00 ?8 ???? 1?? ?01? rev. 1.00 ?9 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. ht46r016 interrupt source priority vector externa? interr?pt 1 04h timer/event counter 0 overfow ? 08h a/d conversion comp?ete 3 0ch time base overfow 4 10h HT46R017 interrupt source priority vector externa? interr?pt 1 04h timer/event counter 0 overfow ? 08h timer/event counter 1 overfow 3 0ch a/d conversion comp?ete 4 10h time base overfow 5 14h in cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced frst. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bit, inte, must frst be set. an actual external interrupt will take place when the external interrupt request fag, intf, is set, a situation that will occur when an edge transition appears on the external int line. the type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the integ0 and integ1 bits, which are bits 6 and 7 respectively, in the ctrl0 control register. these two bits can also disable the external interrupt function. integ1 integ0 edge trigger type 0 0 externa? interr?pt disab?e 0 1 rising edge trigger 1 0 fa?? ing edge trigger 1 1 both edge trigger the external interrupt pin is pin-shared with the i/o pin pa3 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the intc0 register has been set and the edge trigger type has been selected using the ctrl0 register. the pin must also be setup as an input by setting the corresponding pac.3 bit in the port control register. when the interrupt is enabled, the stack is not full and a transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request fag, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input.
rev. 1.00 ?8 ???? 1?? ?01? rev. 1.00 ?9 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, tne, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request fag, tnf, is set, a situation that will occur when the relevant timer/event counter overfows. when the interrupt is enabled, the stack is not full and a timer/event counter overfow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request fag, tnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. time base interrupts for a time base interrupt to occur the global interrupt enable bit emi and the corresponding interrupt enable bit tbe, must first be set. an actual time base interrupt will take place when the time base request fag tbf is set, a situation that will occur when the time base overfows. when the interrupt is enabled, the stack is not full and a time base overfow occurs a subroutine call to time base vector will take place. when the interrupt is serviced, the time base interrupt fag. tbf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the power down mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the power down mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the power down mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.00 70 ???? 1?? ?01? rev. 1.00 71 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by a software instruction. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a "call subroutine" is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 ?vwhprvfloodwrufrq?xudwlrq+;7ru+?5& ? hirc freq?enc? se?ection: 4mhz? 8mhz or 1?mhz. application circuits

rev. 1.00 70 ???? 1?? ?01? rev. 1.00 71 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 7? ???? 1?? ?01? rev. 1.00 73 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low us ing either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 7? ???? 1?? ?01? rev. 1.00 73 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[m] add data memor? to acc 1 z? c? ac? ov addm a?[m] add acc to data memor ? 1 note z? c? ac? ov add a?x add immediate data to acc 1 z? c? ac? ov adc a?[m] add data memor? to acc with carr? 1 z? c? ac? ov adcm a?[m] add acc to data memor ? with carr? 1 note z? c? ac? ov sub a?x s? btract immediate data from the acc 1 z? c? ac? ov sub a?[m] s?btract data memor? from acc 1 z? c? ac? ov subm a?[m] s?btract data memor? from acc with res??t in data memor? 1 note z? c? ac? ov sbc a?[m] s?btract data memor? from acc with carr? 1 z? c? ac? ov sbcm a?[m] s?btract data memor? from acc with carr ?? res??t in data memor? 1 note z? c? ac? ov daa [m] decima? adj? st acc for addition with res??t in data memor? 1 note c logic operation and a?[m] logica? and data memor? to acc 1 z or a?[m] logica? or data memor? to acc 1 z xor a?[m] logica? xor data memor? to acc 1 z andm a?[m] logica? and acc to data memor? 1 note z orm a?[m] logica? or acc to data memor? 1 note z xorm a?[m] logica? xor acc to data memor? 1 note z and a?x logica? and immediate data to acc 1 z or a?x logica? or immediate data to acc 1 z xor a?x logica? xor immediate data to acc 1 z cpl [m] comp?ement data memor? 1 note z cpla [m] comp?ement data memor? with res?? t in acc 1 z increment & decrement inca [m] increment data memor? with res?? t in acc 1 z inc [m] increment data memor? 1 note z deca [m] decrement data memor? with res?? t in acc 1 z dec [m] decrement data memor? 1 note z rotate rra [m] rotate data memor? right with res?? t in acc 1 none rr [m] rotate data memor? right 1 note none rrca [m] rotate data memor? right thro?gh carr? with res?? t in acc 1 c rrc [m] rotate data memor? right thro?gh carr? 1 note c rla [m] rotate data memor? ?eft with res?? t in acc 1 none rl [m] rotate data memor? ?eft 1 note none rlca [m] rotate data memor? ?eft thro?gh carr? with res?? t in acc 1 c rlc [m] rotate data memor? ?eft thro?gh carr? 1 note c
rev. 1.00 74 ???? 1?? ?01? rev. 1.00 75 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu mnemonic description cycles flag affected data move mov a ?[m] move data memor? to acc 1 none mov [m]?a move acc to data memor ? 1 note none mov a ?x move immediate data to acc 1 none bit operation clr [m].i c?ear bit of data memor? 1 note none set [m].i set bit of data memor? 1 note none branch ? mp addr ??mp ?nconditiona??? ? none sz [m] skip if data memor? is zero 1 note none sza [m] skip if data memor? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memor? is zero 1 note none snz [m].i skip if bit i of data memor? is not zero 1 note none siz [m] skip if increment data memor? is zero 1 note none sdz [m] skip if decrement data memor? is zero 1 note none siza [m] skip if increment data memor? is zero with res?? t in acc 1 note none sdza [m] skip if decrement data memor? is zero with res?? t in acc 1 note none call addr s?bro?tine ca?? ? none ret ret?rn from s?bro?tine ? none ret a ?x ret?rn from s?bro?tine and ? oad immediate data to acc ? none reti ret?rn from interr?pt ? none table read tabrd [m] read tab? e to tblh and data memor? ? note none tabrdl [m] read tab?e (? ast page) to tblh and data memor? ? note none miscellaneous nop no operation 1 none clr [m] c?ear data memor? 1 note none set [m] set data memor? 1 note none clr wdt c? ear watchdog timer 1 to ? pdf clr wdt1 pre-c? ear watchdog timer 1 to ? pdf clr wdt? pre-c? ear watchdog timer 1 to ? pdf swap [m] swap nibb?es of data memor? 1 note none swapa [m] swap nibb?es of data memor? with res?? t in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 74 ???? 1?? ?01? rev. 1.00 75 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu instruction defnition add data memor? to acc with carr? the contents of the specifed data memory, accumulator and the carry fag are added. the res ?? t is stored in the acc?m?? ator. acc acc + [m] + c ov ? z? ac? c add acc to data memor ? with carr? the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. [m] acc + [m] + c ov ? z? ac? c add data memor? to acc the contents of the specifed data memory and the accumulator are added. the res?? t is stored in the acc?m?? ator. acc acc + [m] ov ? z? ac? c add immediate data to acc the contents of the accumulator and the specifed immediate data are added. the res?? t is stored in the acc?m?? ator. ac acc + x ov ? z? ac? c add acc to data memor ? the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. [m] acc + [m] ov ? z? ac? c logica? and data memor? to acc data in the accumulator and the specifed data memory perform a bitwise logical and operation. the res ?? t is stored in the acc?m?? ator. acc acc and [m] z logica? and immediate data to acc data in the acc ?m?? ator and the specified immediate data perform a bitwise ?ogica? and operation. the res?? t is stored in the acc?m?? ator. acc acc and x z logica? and acc to data memor? data in the specifed data memory and the accumulator perform a bitwise logical and operation. the res ??t is stored in the data memor? . [m] acc and [m] z adc a,[m] description operation affected fag(s) adcm a,[m] description operation affected fag(s) add a,[m] description operation affected fag(s) add a,x description operation affected fag(s) addm a,[m] description operation affected fag(s) and a,[m] description operation affected fag(s) and a,x description operation affected fag(s) andm a,[m] description operation affected fag(s)
rev. 1.00 7? ???? 1?? ?01? rev. 1.00 77 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu s?bro?tine ca?? unconditionally calls a subroutine at the specifed address. the program counter then increments b ? 1 to obtain the address of the next instr ? ction which is then p? shed onto the stack. the specified address is then ? oaded and the program contin ? es exec ? tion from this new address. as this instr ? ction req ? ires an additiona? operation? it is a two c?c?e instr?ction. stack program co?nter + 1 program co?nter addr none c?ear data memor? each bit of the specifed data memory is cleared to 0. [m] 00h none c?ear bit of data memor? bit i of the specifed data memory is cleared to 0. [m].i 0 none c? ear watchdog timer the to, pdf fags and the wdt are all cleared. wdt c ?eared to 0 pdf 0 to ? pdf pre-c? ear watchdog timer the to, pdf fags and the wdtare all cleared. note that this instruction works in conj? nction with clr wdt? and m? st be exec? ted a?ternate?? with clr wdt? to have effect. repetitive ?? exec? ting this instr? ction witho? t a?ternate?? exec?ting clr wdt? wi?? have no effect. wdt c ?eared to 0 pdf 0 to ? pdf pre-c? ear watchdog timer the to, pdf fags and the wdtare all cleared. note that this instruction works in conj? nction with clr wdt1 and m? st be exec? ted a?ternate?? with clr wdt1 to have effect. repetitive ?? exec? ting this instr? ction witho? t a?ternate?? exec?ting wdt c ?eared to 0 pdf 0 to ? pdf call addr description operation affected fag(s) clr [m] description operation affected fag(s) clr [m].i description operation affected fag(s) clr wdt description operation affected fag(s) clr wdt1 description operation affected fag(s) clr wdt2 description operation affected fag(s)
rev. 1.00 7? ???? 1?? ?01? rev. 1.00 77 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu comp?ement data memor? each bit of the specified data memor ? is ?ogica??? comp? emented (1 ' s comp ? ement). bits which previo?s ?? contained a 1 are changed to 0 and vice versa. [m] [m] z comp?ement data memor? with res?? t in acc each bit of the specified data memor ? is ?ogica??? comp? emented (1 ' s comp ? ement). bits which previo?s ?? contained a 1 are changed to 0 and vice versa. the comp ? emented res?? t is stored in the acc?m??ator and the contents of the data memor? remain ?nchanged. acc [m] z decima?-adj? st acc for addition with res??t in data memor? convert the contents of the acc ?m??ator va?? e to a bcd ( binar? coded decima?) va??e res?? ting from the previo? s addition of two bcd variab? es. if the ?ow nibb?e is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibb? e. otherwise the ? ow nibb? e remains ? nchanged. if the high nibb? e is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentia ???? the decima? conversion is performed b? adding 00h? 0?h? ? 0h or 66h depending on the accumulator and fag conditions. only the c fag may be affected b ? this instr? ction which indicates that if the origina? bcd s?m is greater than 100? it a??ows m??tip?e precision decima? addition. [m] acc + 00h or [m] acc + 0 ?h or [m] acc + ?0h or [m] acc + ??h c decrement data memor? data in the specifed data memory is decremented by 1. [m] [m] D 1 z decrement data memor? with res?? t in acc data in the specifed data memory is decremented by 1. the result is stored in the acc ?m?? ator. the contents of the data memor? remain ?nchanged. acc [m] D 1 z cpl [m] description operation affected fag(s) cpla [m] description operation affected fag(s) daa [m] description operation affected fag(s) dec [m] description operation affected fag(s) deca [m] description operation affected fag(s)
rev. 1.00 78 ???? 1?? ?01? rev. 1.00 79 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu enter power down mode this instr?ction stops the program exec?tion and t? rns off the s? stem c? ock. the contents of the data memor ? and registers are retained. the wdt and presca?er are c ? eared. the power down f? ag pdf is set and the wdt time-o? t f? ag to is c?eared. to 0 pdf 0 to ? pdf increment data memor? data in the specifed data memory is incremented by 1. [m] [m]+1 z increment data memor? with res?? t in acc data in the specifed data memory is incremented by 1. the result is stored in the acc?m?? ator. the contents of the data memor? remain ?nchanged. acc [m]+1 z ??mp ?nconditiona??? the contents of the program co ? nter are rep? aced with the specified address. program exec ? tion then contin ? es from this new address. as this req ? ires the insertion of a d ?mm? instr?ction whi?e the new address is ?oaded? it is a two c?c?e instr?ction. program co?nter addr none move data memor? to acc the contents of the specifed data memory are copied to the accumulator. acc [m] none move immediate data to acc the immediate data specifed is loaded into the accumulator. acc x none move acc to data memor ? the contents of the accumulator are copied to the specifed data memory. [m] acc none no operation no operation is performed. exec?tion contin?es with the next instr?ction. no operation none halt description operation affected fag(s) inc [m] description operation affected fag(s) inca [m] description operation affected fag(s) jmp addr description operation affected fag(s) mov a,[m] description operation affected fag(s) mov a,x description operation affected fag(s) mov [m],a description operation affected fag(s) nop description operation affected fag(s)
rev. 1.00 78 ???? 1?? ?01? rev. 1.00 79 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu logica? or data memor? to acc data in the accumulator and the specifed data memory perform a bitwise logical or operation. the res ?? t is stored in the acc?m?? ator. acc acc " or " [m] z logica? or immediate data to acc data in the acc ?m?? ator and the specified immediate data perform a bitwise ?ogica? or operation. the res?? t is stored in the acc?m?? ator. acc acc " or " x z logica? or acc to data memor? data in the specifed data memory and the accumulator perform a bitwise logical or operation. the res ??t is stored in the data memor? . [m] acc " or " [m] z ret?rn from s?bro?tine the program co? nter is restored from the stack. program exec?tion contin?es at the restored address. program co?nter stack none ret?rn from s?bro?tine and ? oad immediate data to acc the program co? nter is restored from the stack and the acc?m??ator ? oaded with the specifed immediate data. program execution continues at the restored address. program co?nter stack acc x none ret?rn from interr?pt the program co? nter is restored from the stack and the interr?pts are re-enab?ed b? setting the emi bit. emi is the master interr?pt g?oba? enab? e bit. if an interr?pt was pending when the reti instr ? ction is exec?ted? the pending interr?pt ro?tine wi?? be processed before ret?rning to the main program. program co?nter stack emi 1 none rotate data memor? ?eft the contents of the specified data memor ? are rotated ? eft b ? 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~?) [m].0 [m].7 none or a,[m] description operation affected fag(s) or a,x description operation affected fag(s) orm a,[m] description operation affected fag(s) ret description operation affected fag(s) ret a,x description operation affected fag(s) reti description operation affected fag(s) rl [m] description operation affected fag(s)
rev. 1.00 80 ???? 1?? ?01? rev. 1.00 81 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu . rotate data memor? ?eft with res?? t in acc the contents of the specified data memor? are rotated ?eft b? 1 bit with bit 7 rotated into bit 0. the rotated res ?? t is stored in the acc?m?? ator and the contents of the data memor? remain ?nchanged. acc.(i+1) [m].i; (i = 0~?) acc.0 [m].7 none rotate data memor? ?eft thro?gh carr? the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~?) [m].0 c c [m].7 c rotate data memor? ?eft thro?gh carr? with res?? t in acc data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated res?? t is stored in the acc?m?? ator and the contents of the data memor? remain ?nchanged. acc.(i+1) [m].i; (i = 0~?) acc.0 c c [m].7 c rotate data memor? right the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~?) [m].7 [m].0 none rotate data memor? right with res?? t in acc data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated res ?? t is stored in the acc?m?? ator and the contents of the data memor? remain ?nchanged. acc.i [m].(i+1); (i = 0~?) acc.7 [m].0 none rotate data memor? right thro?gh carr? the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. [m].i [m].(i+1); (i = 0~?) [m].7 c c [m].0 c rla [m] description operation affected fag(s) rlc [m] description operation affected fag(s) rlca [m] description operation affected fag(s) rr [m] description operation affected fag(s) rra [m] description operation affected fag(s) rrc [m] description operation affected fag(s)
rev. 1.00 80 ???? 1?? ?01? rev. 1.00 81 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu rotate data memor? right thro?gh carr? with res?? t in acc data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated res?? t is stored in the acc?m?? ator and the contents of the data memor? remain ?nchanged. acc.i [m].(i+1); (i = 0~?) acc.7 c c [m].0 c s?btract data memor? from acc with carr? the contents of the specifed data memory and the complement of the carry fag are s? btracted from the acc?m?? ator. the res?? t is stored in the acc?m?? ator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc D [m] D c ov ? z? ac? c s?btract data memor? from acc with carr? and res??t in data memor? the contents of the specifed data memory and the complement of the carry fag are s? btracted from the acc?m?? ator. the res?? t is stored in the data memor? . note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc D [m] D c ov ? z? ac? c skip if decrement data memor? is 0 the contents of the specifed data memory are frst decremented by 1. if the result is 0 the fo?? owing instr? ction is skipped. as this req? ires the insertion of a d?mm? instr?ction whi?e the next instr?ction is fetched? it is a two c?c?e instr? ction. if the res??t is not 0 the program proceeds with the fo??owing instr?ction. [m] [m] D 1 skip if [m] = 0 none skip if decrement data memor? is zero with res?? t in acc the contents of the specifed data memory are frst decremented by 1. if the result is 0? the fo?? owing instr? ction is skipped. the res?? t is stored in the acc?m?? ator but the specifed data memory contents remain unchanged. as this requires the insertion of a d ?mm? instr?ction whi? e the next instr? ction is fetched? it is a two c?c? e instr? ction. if the res?? t is not 0 ? the program proceeds with the fo ?? owing instr?ction. acc [m] D 1 skip if acc = 0 none rrca [m] description operation affected fag(s) sbc a,[m] description operation affected fag(s) sbcm a,[m] description operation affected fag(s) sdz [m] description operation affected fag(s) sdza [m] description operation affected fag(s)
rev. 1.00 8? ???? 1?? ?01? rev. 1.00 83 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu set data memor? each bit of the specifed data memory is set to 1. [m] ffh none set bit of data memor? bit i of the specifed data memory is set to 1. [m].1 1 none skip if increment data memor? is 0 the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo?? owing instr? ction is skipped. as this req? ires the insertion of a d?mm? instr?ction whi? e the next instr? ction is fetched? it is a two c?c?e instr? ction. if the res??t is not 0 the program proceeds with the fo??owing instr?ction. [m] [m] + 1 skip if [m] = 0 none skip if increment data memor? is zero with res?? t in acc the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo??owing instr? ction is skipped. the res?? t is stored in the acc?m?? ator but the specifed data memory contents remain unchanged. as this requires the insertion of a d ?mm? instr? ction whi? e the next instr? ction is fetched? it is a two c?c?e instr? ction. if the res?? t is not 0 the program proceeds with the fo?? owing instr?ction. acc [m] + 1 skip if acc = 0 none skip if bit i of data memor? is not 0 if bit i of the specifed data memory is not 0, the following instruction is skipped. as this req?ires the insertion of a d?mm? instr?ction whi?e the next instr?ction is fetched? it is a two c?c? e instr? ction. if the res?? t is 0 the program proceeds with the fo??owing instr?ction. skip if [m].i 0 none s?btract data memor? from acc the specifed data memory is subtracted from the contents of the accumulator. the res ?? t is stored in the acc ? m ?? ator. note that if the res ?? t of s? btraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc D [m] ov ? z? ac? c set [m] description operation affected fag(s) set [m].i description operation affected fag(s) siz [m] description operation affected fag(s) siza [m] description operation affected fag(s) snz [m].i description operation affected fag(s) sub a,[m] description operation affected fag(s)
rev. 1.00 8? ???? 1?? ?01? rev. 1.00 83 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu s?btract data memor? from acc with res??t in data memor? the specifed data memory is subtracted from the contents of the accumulator. the res?? t is stored in the data memor? . note that if the res ??t of s? btraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. [m] acc D [m] ov ? z? ac? c s? btract immediate data from acc the immediate data specifed by the code is subtracted from the contents of the acc ?m ?? ator. the res?? t is stored in the acc?m?? ator. note that if the res ?? t of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc D x ov ? z? ac? c swap nibb?es of data memor? the ? ow-order and high-order nibb? es of the specified data memor? are interchanged. [m].3~[m].0?[m].7 ~ [m].4 none swap nibb?es of data memor? with res?? t in acc the ? ow-order and high-order nibb? es of the specified data memor? are interchanged. the res ?? t is stored in the acc?m?? ator. the contents of the data memor? remain ?nchanged. acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 none skip if data memor? is 0 if the contents of the specified data memor ? is 0? the fo ?? owing instr? ction is skipped. as this req ?ires the insertion of a d?mm? instr?ction whi? e the next instr?ction is fetched? it is a two c?c?e instr?ction. if the res??t is not 0 the program proceeds with the fo??owing instr?ction. skip if [m] = 0 none skip if data memor? is 0 with data movement to acc the contents of the specifed data memory are copied to the accumulator. if the va?? e is zero? the fo?? owing instr? ction is skipped. as this req? ires the insertion of a d?mm? instr?ction whi? e the next instr? ction is fetched? it is a two c?c?e instr?ction. if the res??t is not 0 the program proceeds with the fo??owing instr?ction. acc [m] skip if [m] = 0 none subm a,[m] description operation affected fag(s) sub a,x description operation affected fag(s) swap [m] description operation affected fag(s) swapa [m] description operation affected fag(s) sz [m] description operation affected fag(s) sza [m] description operation affected fag(s)
rev. 1.00 84 ???? 1?? ?01? rev. 1.00 85 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu skip if bit i of data memor? is 0 if bit i of the specifed data memory is 0, the following instruction is skipped. as this req ? ires the insertion of a d?mm? instr ? ction whi? e the next instr? ction is fetched? it is a two c?c?e instr?ction. if the res??t is not 0? the program proceeds with the fo??owing instr?ction. skip if [m].i = 0 none read tab? e to tblh and data memor? the program code addressed b ? the tab? e pointer (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] program code (?ow b?te) tblh program code (high b?te) none read tab?e (? ast page) to tblh and data memor? the ? ow b? te of the program code ( ? ast page) addressed b? the tab ? e pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] program code (?ow b?te) tblh program code (high b?te) none logica? xor data memor? to acc data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the res ?? t is stored in the acc?m?? ator. acc acc " xor " [m] z logica? xor acc to data memor? data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the res ??t is stored in the data memor? . [m] acc " xor " [m] z logica? xor immediate data to acc data in the acc ?m?? ator and the specified immediate data perform a bitwise ?ogica? xor operation. the res?? t is stored in the acc?m?? ator. acc acc " xor " x z sz [m].i description operation affected fag(s) tabrd [m] description operation affected fag(s) tabrdl [m] description operation affected fag(s) xor a,[m] description operation affected fag(s) xorm a,[m] description operation affected fag(s) xor a,x description operation affected fag(s)
rev. 1.00 84 ???? 1?? ?01? rev. 1.00 85 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0.780 0.880 b 0.?40 0.?80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0?? f 0.045 0.070 g 0.100 h 0.300 0.3?5 i 0.430 symbol dimensions in mm min. nom. max. a 19.81 ??.35 b ?.10 7.11 c ?.9? 4.95 d ?.9? 3.81 e 0.3? 0.5? f 1.14 1.78 g ?.54 h 7.?? 8.?? i 10.9?
rev. 1.00 8? ???? 1?? ?01? rev. 1.00 87 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 0.735 0.775 b 0.?40 0.?80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0?? f 0.045 0.070 g 0.100 h 0.300 0.3?5 i 0.430 symbol dimensions in mm min. nom. max. a 18.?7 19.?9 b ?.10 7.11 c ?.9? 4.95 d ?.9? 3.81 e 0.3? 0.5? f 1.14 1.78 g ?.54 h 7.?? 8.?? i 10.9?
rev. 1.00 8? ???? 1?? ?01? rev. 1.00 87 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 0.745 0.785 b 0.?75 0.?95 c 0.1?0 0.150 d 0.110 0.150 e 0.014 0.0?? f 0.045 0.0?0 g 0.100 h 0.300 0.3?5 i 0.430 symbol dimensions in mm min. nom. max. a 18.9? 19.94 b ?.99 7.49 c 3.05 3.81 d ?.79 3.81 e 0.3? 0.5? f 1.14 1.5? g ?.54 h 7.?? 8.?? i 10.9?
rev. 1.00 88 ???? 1?? ?01? rev. 1.00 89 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.??8 0.?44 b 0.150 0.157 c 0.01? 0.0?0 c 0.38? 0.40? d 0.0?9 e 0.050 f 0.004 0.010 g 0.01? 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 ?.?0 b 3.81 3.99 c 0.30 0.51 c 9.80 10.?1 d 1.75 e 1.?7 f 0.10 0.?5 g 0.41 1.?7 h 0.18 0.?5 0 8
rev. 1.00 88 ???? 1?? ?01? rev. 1.00 89 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu reel dimensions sop 16nsop (150mil) symbol description dimensions in mm a ree? o?ter diameter 330 .0 1.0 b ree? inner diameter 100.0 1.5 c spind?e ho?e diameter 13.0 +0.5/-0.? d ke? s?it width ? .0 0.5 t1 space between f?ange 1?.8 +0.3/-0.? t? ree? thickness ??.?0.?
rev. 1.00 90 ???? 1?? ?01? rev. 1.00 91 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d type 8-bit otp mcu carrier tape dimensions 16-pin nsop (150mil) symbol description symbol description dimensions in mm w carrier tape width 1? .0 0.3 p cavit? pitch 8 .0 0.1 e perforation position 1.75 0.1 f cavit? to perforation (width direction) 7 .5 0.1 d perforation diameter 1.5 5 +0.1 0/-0.00 d1 cavit? ho?e diameter 1.5 0 +0.?5 /-0.00 p0 perforation pitch 4.0 0.1 p1 cavit? to perforation (length direction) ?.0 0.1 a0 cavit? length ?.5 0.1 b0 cavit? width 10.3 0.1 k0 cavit? depth ?.1 0.1 t carrier tape thickness 0.30 0.0 5 c cover tape width 13.3 0.1
rev. 1.00 90 ???? 1?? ?01? rev. 1.00 91 ???? 1?? ?01? ht46r016/HT46R017 enhanced a/d 8-bit otp mcu holtek semiconductor inc. (headquarters) no.3? creation rd. ii? science park? hsinch?? taiwan te ?: 88?-3-5?3-1999 fax: 88?-3-5? 3-1189 http://www.ho ?tek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. 3-?? y ?anq? st.? nankang software park? taipei 115? taiwan te ?: 88?-?-??55-7070 fax: 88?-?-??55-7373 fax: 88?-?-??55-7383 (internationa? sa?es hot?ine) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a? prod?ctivit? b?i?ding? no.5 gaoxin m ?nd road? nanshan district? shenzhen? china 518057 te ?: 8?-755-8?1?-9908? 8?-755-8?1?-9308 fax: 8?-755-8?1?-97?? holtek semiconductor (usa), inc. (north america sales offce) 4?7?9 fremont b?vd.? fremont? ca 94538? usa te ?: 1-510-?5?-9880 fax: 1-510-?5?-9885 http://www.ho ?tek.com cop?right ? ?01? b? holtek semiconductor inc. the information appearing in this data sheet is be ? ieved to be acc? rate at the time of p?b? ication. however ? ho? tek ass ? mes no responsibi?it ? arising from the ? se of the specifications described. the app?ications mentioned herein are ?sed so?e?? for the p?rpose of i???stration and ho? tek makes no warrant ? or representation that s?ch app? ications wi?? be s? itab? e witho? t f ? rther modification? nor recommends the ? se of its prod? cts for app? ication that ma? present a risk to h?man ? ife d? e to ma?f?nction or otherwise. ho?tek's prod?cts are not a?thorized for ?se as critica? components in ? ife support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most ?p-to-date information? p?ease visit o?r web site at http://www.ho ?tek.com.tw .

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